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In the Proceedings of The 32nd International Symposium on Computer Architecture (ISCA'05), June 2005. Exploiting Structural Duplication for Lifetime Reliability Enhancement
 

Summary: In the Proceedings of The 32nd International Symposium on Computer Architecture (ISCA'05), June 2005.
Exploiting Structural Duplication for Lifetime Reliability Enhancement
Jayanth Srinivasan, Sarita V. Adve Pradip Bose, Jude A. Rivers
University of Illinois at Urbana-Champaign IBM T.J. Watson Research Center
Department of Computer Science Yorktown Heights,NY
srinivsn,sadve @cs.uiuc.edu, pbose,jarivers @us.ibm.com
Abstract
Increased power densities (and resultant temperatures)
and other effects of device scaling are predicted to cause
significant lifetime reliability problems in the near future.
In this paper, we study two techniques that leverage mi-
croarchitectural structural redundancy for lifetime reliabil-
ity enhancement. First, in structural duplication (SD),
redundant microarchitectural structures are added to the
processor and designated as spares. Spare structures can
be turned on when the original structure fails, increasing
the processor's lifetime. Second, graceful performance
degradation (GPD) is a technique that exploits existing
microarchitectural redundancy for reliability. Redundant
structures that fail are shut down while still maintaining

  

Source: Adve, Sarita - Department of Computer Science, University of Illinois at Urbana-Champaign

 

Collections: Computer Technologies and Information Sciences