Summary: On the Design and Implementation of a Cache­Aware Multicore
Real­Time Scheduler #
John M. Calandrino and James H. Anderson
Department of Computer Science, The University of North Carolina at Chapel Hill
Abstract
Multicore architectures, which have multiple processing
units on a single chip, have been adopted by most chip man­
ufacturers. Most such chips contain on­chip caches that are
shared by some or all of the cores on the chip. Prior work has
presented methods for improving the performance of such
caches when scheduling soft real­time workloads. Given
these methods, two additional research issues arise: (1) how
to automatically profile the cache behavior of real­time tasks
within the scheduler; and (2) how to implement scheduling
methods efficiently, so that scheduling overheads do not off­
set any cache­related performance gains. This paper ad­
dresses these two issues in an implementation of a cache­
aware soft real­time scheduler within Linux, and shows that
the use of this scheduler can result in performance improve­
ments that directly result from a decrease in shared cache

Source: Anderson, James - Department of Computer Science, University of North Carolina at Chapel Hill

Collections: Computer Technologies and Information Sciences