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Low Power IP Design Methodology for Rapid Development of DSP Intensive SOC Platforms
 

Summary: 1
Low Power IP Design Methodology for Rapid Development
of DSP Intensive SOC Platforms
T. Arslan, A. T. Erdogan, S.Masupe, C. Chun­Fu, and D. Thompson
Edinburgh University
Kings Buildings
Mayfield Road
Edinburgh EH9 3JL
Abstract
The work presents a design methodology for the development of IPs specially optimised for
computationally intensive portable systems, where power saving is a prime target. The
methodology is based on implementation algorithms, developed at Edinburgh University,
which are inherently power optimal. Power reduction is achieved by reducing the effective
switched capacitance of the system. Hence the IPs can be used alongside conventional power
saving approaches such as supply voltage reduction and clock gating for greater savings in
power. The reduction in switched capacitance is achieved by a combination of reducing the
switching activity during multiplication operations and reducing memory access. This makes
the IPs ideal for operation in System­On­Chip applications and Integration Platform based
derivative design environment, where bus operations contribute to significant proportion of
the amount of switching power. This in turn makes them invaluable for applications with fast

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering