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Summary: The Impact of Non-coherent Buffers on
Lazy Hardware Transactional Memory Systems
Anurag Negi
Rub´en Titos-Gil
Manuel E. Acacio
Jos´e M. Garc´ia
Per Stenstrom
Universidad de Murcia
Chalmers University of Technology
{rtitos,meacacio,jmgarcia}@ditec.um.es
{negi,per.stenstrom}@chalmers.se
Abstract
When supported in silicon, transactional memory
(TM) promises to become a fast, simple and scal-
able parallel programming paradigm for future shared
memory multiprocessor systems. Among the multitude
of hardware TM design points and policies that have
been studied so far, lazy conflict resolution designs
often extract the most concurrency, but their inherent
need for lazy versioning requires careful management
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