Home

About

Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network
FAQHELPSITE MAPCONTACT US


  Advanced Search  

 
126 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 31, NO. 00, 2008 High Performance Inductors on CMOS-Grade
 

Summary: 126 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 31, NO. 00, 2008
High Performance Inductors on CMOS-Grade
Trenched Silicon Substrate
Mina Rais-Zadeh, Student Member, IEEE, Joy Laskar, Fellow, IEEE, and Farrokh Ayazi, Senior Member, IEEE
Abstract--This paper reports on a new implementation of
high-quality factor copper inductors on CMOS-grade silicon sub-
strates ( = 10-20
cm) using a CMOS-compatible process.
A low-temperature fabrication sequence ( 300 C) is used to
reduce the loss in silicon at RF frequencies by trenching the silicon
substrate. The high aspect-ratio (30:1) trenches are subsequently
bridged over or refilled with a low-loss dielectric to close the open
areas and create a rigid low-loss island, referred to as Trenched
Si Island. This method does not require air suspension of the
inductors, resulting in mechanically-robust structures that are
compatible with any packaging technology. A one-turn 0.8 nH
inductor fabricated on a Trenched Silicon Island exhibits a very
high peak quality factor of 71 at 8.75 GHz with a self-resonant
frequency larger than 15 GHz.
Index Terms--CMOS compatible, high- inductors, low-loss

  

Source: Ayazi, Farrokh - School of Electrical and Computer Engineering, Georgia Institute of Technology

 

Collections: Engineering