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Appears in, The 31st Annual International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004 The Vector-Thread Architecture
 

Summary: Appears in, The 31st Annual International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004
The Vector-Thread Architecture
Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding,
Brian Pharris, Jared Casper, and Krste Asanovi´c
MIT Computer Science and Artificial Intelligence Laboratory, 32 Vassar Street, Cambridge, MA 02139
ronny,cbatten,krsteˇ @csail.mit.edu
Abstract
The vector-thread (VT) architectural paradigm unifies the vector
and multithreaded compute models. The VT abstraction provides
the programmer with a control processor and a vector of virtual
processors (VPs). The control processor can use vector-fetch com-
mands to broadcast instructions to all the VPs or each VP can use
thread-fetches to direct its own control flow. A seamless intermix-
ing of the vector and threaded control mechanisms allows a VT ar-
chitecture to flexibly and compactly encode application parallelism
and locality, and a VT machine exploits these to improve perfor-
mance and efficiency. We present SCALE, an instantiation of the
VT architecture designed for low-power and high-performance em-
bedded systems. We evaluate the SCALE prototype design using
detailed simulation of a broad range of embedded applications and

  

Source: Asanović, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

 

Collections: Computer Technologies and Information Sciences