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A 32nm and 0.9V CMOS Phase-Locked Loop with Leakage Current and Power Supply Noise Compensation

Summary: 1
A 32nm and 0.9V CMOS Phase-Locked Loop with
Leakage Current and Power Supply Noise Compensation
Kyung Ki Kim, Yong-Bin Kim
Department of Electrical and Computer Engineering
Northeastern University, Boston, MA, USA
E-mail: kkkim@ece.neu.edu, ybk@ece.neu.edu
Abstract - This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in
phase locked loop (PLL) using nanometer CMOS technology. The leakage compensation circuit reduces the leakage
current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold
voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation
on the output frequency of VCO. The PLL design is based on 32nm predictive CMOS technology and uses 0.9V power
supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440MHz output
frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply
voltage variations. The PLL has an output frequency range of 40M~725MHz with a multiplication range of 1-1023, and
the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.
Keywords: Nanometer CMOS, Leakage Current, Power Supply Noise, Phase-Locked Loop (PLL)
I. Introduction
The strong demand for low-power computing has been driven by a growing variety of portable and battery-
operated electronic devices. These span a broad range of performance and functions with respect to throughput.


Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University


Collections: Engineering