Summary: Beitrag zum GI/ITG­Workshop Anwenderprogrammierbare Schaltungen, 23./24. Juni 1994, Karlsruhe.
Keywords: Systolic Computing, Self Arbitrating Dataflow, Pipeline Architectures,
Field Programmable Gate Arrays.
Self Arbitrating Elements for Modelling Systolic
Dataflow in Field Programmable Gate Arrays
Dr.­Ing. Bernhard Lang
TU Hamburg­Harburg
Technische Informatik I
Harburger Schloßstraße 20 email: lang@tu­harburg.d400.de
21071 Hamburg Phone: +40/7718­2786
GERMANY FAX: +40/7718­2911
Introduction
In low level signal and image processing and in telecommunication applications a huge
amount of data has to be processed. The processing demands still reach the limits of
modern general purpose and signal processors thus a processing support by flexible hard­
ware is desirable in this area. The described demands lead to systolic computing [1] with
data ``flowing'' through processing networks. Todays field programmable logic devices can
serve for this function offering a programmable low level processing hardware modelling
this low level processing dataflow [2, 3].
Following the low level steps computations with more complex and data dependent algo­

Source: Albert-Ludwigs-Universität Freiburg, Institut für Informatik,, Lehrstuhls für Mustererkennung und Bildverarbeitung

Collections: Computer Technologies and Information Sciences