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A TRIPLEPORT RAM BASED LOW POWER COMMUTATOR ARCHITECTURE FOR A PIPELINEDFFT PROCESSOR
 

Summary: A TRIPLEPORT RAM BASED LOW POWER COMMUTATOR
ARCHITECTURE FOR A PIPELINEDFFT PROCESSOR
Mohd. Hasan, Tughrul Arslan
Department of Electronics and Electrical Engineering,
The University of Edinburgh,
Edinburgh EH9 3JL, UK
ABSTRACT
This paper proposes a low power commutator architecture
based on triple port RAMs rather than dual port RAMs or
conventional FIFO.forthe radix-4 pipelined FFTprocessor
implementation. The triple port RAM based commutator
consumes less power than the other two for the first and
second stages of a 64-point radix-4 pipelined FFT
processor. This commutator is attractive for shorter FFT's
but can also he used in the last stages of longer FIT'S.Up
to 29% and 9% power savings is achieved for the 8-12 hit
data range in the second and first stages of a 64-point F'FT
processor respectively.
1. INTRODUCTION
One of the fastest growing areas in the computing industry

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering