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Figure 1 Schematic of the proposed comparator Offset Voltage Analysis of Dynamic Latched
 

Summary: Figure 1 Schematic of the proposed comparator
Offset Voltage Analysis of Dynamic Latched
Comparator
HeungJun Jeon and Yong-Bin Kim
Department of Electrical and Computer Engineering
Northeastern University
Boston, MA, USA
{hjeon, ybk}@ece.neu.edu
Minsu Choi
Department of Electrical and Computer Engineering
Missouri University of Science & Technology
Rolla, MO, USA
choim@mst.edu
Abstract-- The offset voltage of the dynamic latched comparator
is analyzed in detail, and the dynamic latched comparator
design is optimized for the minimal offset voltage based on the
analysis in this paper. As a result, 1-sigma offset voltage was
reduced from 12.5mV to 6.5mV at the cost of 9% increase of the
power dissipation (152W from 136W). Using a digitally
controlled capacitive offset calibration technique, the offset

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering