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A HIGH RESOLUTION, STICTIONLESS, CMOS COMPATIBLE SOI ACCELEROMETER WITH A LOW NOISE, LOW POWER, 0.25M CMOS INTERFACE
 

Summary: A HIGH RESOLUTION, STICTIONLESS, CMOS COMPATIBLE SOI ACCELEROMETER
WITH A LOW NOISE, LOW POWER, 0.25M CMOS INTERFACE
Babak Vakili Amini, Siavash Pourkamali, and Farrokh Ayazi
School of Electrical and Computer Engineering
Georgia Institute of Technology, Atlanta, GA 30332-0250
Email: vakilia@ece.gatech.edu; Tel: (404) 385-2400; Fax: (404) 894-4700
ABSTRACT
The implementation and characterization of a high
sensitivity silicon-on-insulator (SOI) capacitive
microaccelerometer with sub-25g resolution is presented.
The in-plane accelerometers were fabricated on 40m thick
SOI substrates using a two-mask, dry-release low
temperature process comprising of three plasma etching
steps. The fabricated devices were interfaced with a high
resolution, low noise and low power switched-capacitor
integrated circuit (IC) fabricated in a 2.5V 0.25m N-well
CMOS process. The measured sensitivity is 0.2pF/g and
the output noise floor is 20g/Hz. The total power
consumption is 3mW.
I. INTRODUCTION

  

Source: Ayazi, Farrokh - School of Electrical and Computer Engineering, Georgia Institute of Technology

 

Collections: Engineering