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Summary: High Speed Switch Scheduling for Local Area Networks
Thomas E. Anderson
Computer Science Division
University of California
Berkeley, CA 94720
Susan S. Owicki, James B. Saxe, and Charles P. Thacker
Systems Research Center
Digital Equipment Corporation
Palo Alto, CA 94301
Abstract
Current technology trends make it possible to build communication networks that can sup-
port high performance distributed computing. This paper describes issues in the design of a
prototype switch for an arbitrary topology point-to-point network with link speeds of up to one
gigabit per second. The switch deals in xed-length ATM-style cells, which it can process at a
rate of 37 million cells per second. It provides high bandwidth and low latency for datagram
tra c. In addition, it supports real-time tra c by providing bandwidth reservations with guar-
anteed latency bounds. The key to the switch's operation is a technique called parallel iterative
matching, which can quickly identify a set of con ict-free cells for transmission in a time slot.
Bandwidth reservations are accommodated in the switch by building a xed schedule for trans-
porting cells from reserved ows across the switch parallel iterative matching can ll unused
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