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Summary: Automatic Verification of a Class of
Systolic Circuits
Parosh Abdulla
Department of Computer Systems
Uppsala University
Box 520
S 751 20 Uppsala
Sweden
February 26, 1996
Abstract
Systolic circuits have drawn considerable attention as a means of
implementing parallel algorithms in areas such as linear algebra, sig
nal processing, pattern matching, etc. A systolic circuit is composed
of a number of computation cells which are connected in a regular
pattern. Each cell can perform computations, store data, and com
municate with other cells in the circuit. We present a method for
automatic verification of a class of these circuits. We define a lan
guage to describe implementations and specifications of our class of
circuits, and present a method to automatically check whether a cir
cuit implementation fulfills its specification. The main advantage of
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