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Summary: DVS for On-Chip Bus Designs Based on Timing Error Correction
Himanshu Kaul
Dennis Sylvester David Blaauw Trevor Mudge Todd Austin
Circuit Research Labs, Intel Corporation, Hillsboro, OR-97124, USA
Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI-48109, USA
Abstract
On-chip buses are typically designed to meet performance
constraints at worst-case conditions, including process corner,
temperature, IR-drop, and neighboring net switching pattern. This
can result in significant performance slack at more typical
operating conditions. In this paper, we propose a dynamic voltage
scaling (DVS) technique for buses, based on a double sampling
latch which can detect and correct for delay errors without the
need for retransmission. The proposed approach recovers the
available slack at non-worst-case operating points through more
aggressive voltage scaling and tracks changing conditions by
monitoring the error recovery rate. Voltage margins needed in
traditional designs to accommodate worst-case performance
conditions are therefore eliminated, resulting in a significant
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