Summary: IEEE DESIGN & TEST OF COMPUTERS 0740-7475/96/$05.00 © 1996 IEEE
Vol. 13, No. 1: SPRING 1996, pp. 26-35(Editorial Information: Address questions or comments about this article to
the author at State University of Informatics and Radioectronics of Belarus, Computer Systems Department,
P.Brovki 6, 220027 Minsk, Belarus; prihozhy% email@example.com.)
Net Scheduling in High-Level Synthesis
State University of Informatics and Radioelectronics of Belarus
A new net scheduling and allocation model generates net schedules that minimize either execution time or resources.
The author tested the model within a VHDL-based high-level synthesis system called Ahiles.
IEEE DESIGN & TEST OF COMPUTERS 0740-7475/96/$05.00 © 1996 IEEE
Vol. 13, No. 1: SPRING 1996, pp. 48-57(Editorial Information: Address questions or comments about this article to
the author at Tallinn Technical University, Computer Engineering Dept., Ehitajate tee 5, EE-0026 Tallinn, Estonia;
Test Synthesis with Alternative Graphs
Tallinn Technical University
Alternative graphs provide an efficient, uniform model describing the structure, functions, and faults in a wide class
of digital circuits and for different representation levels. For test pattern generation, they provide a general
theoretical basis for combining high-level approaches, symbolic techniques based on binary decision diagrams, and