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Analysis and Simulation of Jitter for High Speed Channels in VLSI Systems
 

Summary: 1
Analysis and Simulation of Jitter for High Speed Channels
in VLSI Systems
Kyung Ki Kim, Jing Huang, Yong-Bin Kim, and Fabrizio Lombardi
Department of Electronic and Computer Engineering
Northeastern University, Boston, MA, USA
E-mail: {kkkim, hjang, ybk, lombardi}@ece.neu.edu
Indexing terms: Timing Jitter, Jitter Components, Periodic Jitter, Random Jitter, Inter-Symbol Interference,
Duty Cycle Distortion, Serial Data Systems.
Extended Abstract: This paper presents a novel modeling analysis and simulation of jitter for high speed
(several gigabit per second) IO channels in VLSI systems. Jitter components are analyzed and modeled
individually.
As current serial data systems reach rates of several gigabits per second, timing jitter is becoming a
significant source of data errors. Timing jitter (henceforth referred to as jitter) is defined as the deviation
of a signal transition time from the ideal transition time. A correct model and the analysis of jitter are
essential for testing high speed serial data channels.
Many works have been reported on jitter measurement techniques [1][2]. It is relatively simple to
measure each jitter component separately, but it is challenging to measure and analyze multiple jitter
components if they are either simultaneously injected or already present in a signal over a serial channel.
In this paper, a new jitter injection methodology is proposed and the relationship among jitter

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering