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Published in IET Computers & Digital Techniques Received on 13th April 2007
 

Summary: Published in IET Computers & Digital Techniques
Received on 13th April 2007
Revised on 22nd August 2007
doi: 10.1049/iet-cdt:20070055
ISSN 1751-8601
Energy efficient i-cache using multiple line
buffers with prediction
K. Ali1
M. Aboelaze2
S. Datta2
1
School of Computing, Queens University, Kingston, Ontario, Canada
2
Department of Computer Science and Engineering, York University, Toronto, Ontario, Canada
E-mail: aboelaze@cse.yorku.ca
Abstract: Modern microprocessors dedicate a large portion of the chip area to the cache. Decreasing the energy
consumption of the microprocessor, which is a very important design goal especially for small, battery powered,
devices, depends on decreasing the energy consumption of the memory/cache system in the microprocessor. The
authors investigate the energy consumption in caches and present a novel cache architecture for reduced energy
instruction caches. Our cache architecture consists of the L1 cache, multiple line buffers and a prediction

  

Source: Aboelaze, Mokhtar - Department of Computer Science, York University (Toronto)

 

Collections: Computer Technologies and Information Sciences