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Hard and SoftProgrammable, Multithreaded Micronet Architectures D. K. Arvind and S. Zhong
 

Summary: Hard­ and Soft­Programmable, Multithreaded Micronet Architectures
D. K. Arvind and S. Zhong
Institute for Computing Systems Architecture, University of Edinburgh,
Mayfield Road, Edinburgh EH9 3JZ, Scotland.
Email: dka@dcs.ed.ac.uk
Abstract
It is our belief that future SOC devices will be overwhelm­
ingly programmable, consisting of soft­programmable
forms ­ as instruction set architectures, and hard­
programmable forms ­ realised as field programmable
logic. This paper explores an architectural structure which
integrates them both in a micronet­based multithreaded ar­
chitecture.
Keywords: Asynchronous architectures, Micronets, Multi­
threading, Field Programmable Logic
1 Introduction
This paper describes briefly the introduction of hard­
programmability, in the form of field programmable logic,
in a micronet­based multithreaded instruction set architec­
ture [AR99].

  

Source: Arvind, D. K. - School of Informatics, University of Edinburgh

 

Collections: Computer Technologies and Information Sciences