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Low Power IC Design Seminar, 19 January 2001, London, UK. LOW POWER SYSTEM ON CHIP IMPLEMENTATION SCHEME OF DIGITAL FILTERING CORES
 

Summary: Low Power IC Design Seminar, 19 January 2001, London, UK.
1
LOW POWER SYSTEM ON CHIP IMPLEMENTATION SCHEME OF DIGITAL FILTERING CORES
E. P. Zwyssig, A.T. Erdogan, T. Arslan
Department of Electronics and Electrical Engineering, University of Edinburgh,
Kings Buildings, Mayfield Road, Edinburgh, EH9 3JL, Scotland U.K.
Phone: ++44 131 650 1000; Fax: ++44 131 650 5155
erich.zwyssig@ieee.org, {arslan, ate}@ee.ed.ac.uk
1. Abstract
The paper describes a scheme for the implementation of low power cores for hearing aid applications. Power
saving features of the scheme are two fold. The first due to the utilisation of a macro-component framework
which allows the rapid assembly of the cores on easy-to-verify hierarchical plug-in basis. The second is due to
the system-on-chip strategy. The cores are embedded within an ARM-based system-on-chip platform. For this
VSIA compliant wrapper interfaces have been investigated which allow the cores operation in multiple clock
and bus domains. This provides effective power manipulation by power management strategies. The paper
demonstrates the scheme with a number of FIR filtering cores. The cores are assembled with a number of
different macro-components from the wide range available within a rich library which contains a flexible and
synthesisable set of components for computation, memory, decision, and BIST functions.
Keywords: Low Power, IP framework, Digital Filter, Design for Testability (DfT)
2. Motivation

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering