Summary: 1
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Description styles
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Objectives
· Write VHDL descriptions that produce efficient synthesized circuits
­ How Statements Are Mapped to Logic
­ Design Structure
­ Asynchronous Designs
­ Don't Care Inference
­ Synthesis Issues
· General guidelines
­ Minimize the number of instantiations of several large components.
­ Minimize the number of latches or flip-flops
­ Consider collapsing hierarchy.
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Generated logic
Four logic blocks:
· A comparator

Source: Aboulhamid, El Mostapha - Département d'Informatique et recherche opérationnelle, Université de Montréal

Collections: Engineering