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Dual low-power and crosstalk immune encoding scheme for on-chip data buses

Summary: Dual low-power and crosstalk immune
encoding scheme for on-chip data buses
Z. Khan, A.T. Erdogan and T. Arslan
A new encoding scheme is introduced for low-power and crosstalk
immune communication of generic data on long parallel on-chip
buses. The scheme uses a limited weight codebook with one-to-one
data-to-code mapping. The new scheme and its implementation using
a generic system-on-chip platform are described and results are
provided that indicate a 30% saving in total switching activity with
an 8-bit communication example.
Introduction: The scaling of CMOS technology to ultra-deep sub-
micrometre causes the coupled switched capacitance to dominate the
wire-to-substrate capacitance. This coupled capacitance in turn will
lead to crosstalk noise, which is a potential source for delay faults,
logical malfunctions and energy consumption in on-chip communica-
tion. Techniques based on bus invert [1] and the coupling driven bus
invert (CBI) [2] are among those commonly used in the literature for
reducing self and coupled switched capacitance for generic data of
unknown probabilistic information. However, none of the techniques
in the literature is capable of both eliminating worst crosstalk


Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh


Collections: Engineering