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Submission to HPTS 2001 A Storage Model to Bridge the Processor/Memory Speed Gap
 

Summary: Submission to HPTS 2001
A Storage Model to Bridge the Processor/Memory Speed Gap
Anastassia Ailamaki
Carnegie Mellon University
(joint work with David DeWitt and Mark Hill
at the University of Wisconsin-Madison)
1 Introduction
Memory speeds in today's computers have fundamentally lagged behind processor speeds [7]. Today's
memory systems incur access latencies that are up to three orders of magnitude larger than the latency of a
single arithmetic operation. To alleviate the processor/memory performance gap, computer designers
employ a hierarchy of cache memories (e.g., three levels in the recently announced IBM Power 4 proces-
sors), in which each level trades off higher capacity for faster access times. As database applications
become increasingly memory-intensive, high performance database systems must maximize cache utiliza-
tion by keeping data that are likely to be referenced in the cache hierarchy. Ideally, the database application
should run under the illusion that the database is cache-resident, i.e., the processor should never be idle due
to main memory latency.
When optimizing cache utilization, data placement is extremely important. According to earlier studies
[1][3], when running commercial DBMSs on a modern processor, data misses in the cache hierarchy are a
key memory bottleneck and a major reason for processor stalls. Choosing a data placement scheme that
follows the workload's memory access patterns improves spatial locality, which in turn improves cache

  

Source: Ailamaki, Anastassia - School of Computer Science, Carnegie Mellon University

 

Collections: Computer Technologies and Information Sciences