Summary: Appears in: The 29th Annual Int'l Symposium for Computer Architecture (ISCA-29), Anchorage, AK, May 2002
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines
Seongmoo Heo, Kenneth Barr, Mark Hampton, and Krste Asanovi´c
MIT Laboratory for Computer Science
200 Technology Square, Cambridge, MA 02139
E-mail: {heomoo,kbarr,mhampton,krste}@lcs.mit.edu
Abstract
Leakage power is dominated by critical paths, and hence
dynamic deactivation of fast transistors can yield large sav-
ings. We introduce metrics for comparing fine-grain dy-
namic deactivation techniques that include the effects of
deactivation energy and startup latencies, as well as long-
term leakage current. We present a new circuit-level tech-
nique for leakage current reduction, leakage-biased bit-
lines, that has low deactivation energy and fast wakeup
times. We show how this technique can be applied at a
fine grain within an active microprocessor, and how mi-
croarchitectural scheduling policies can improve its perfor-
mance. Using leakage-biased bitlines to deactivate SRAM
read paths within I-cache memories saves over 24% of leak-

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

Collections: Computer Technologies and Information Sciences