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To appear in the Proceedings of the 1990 International Conference on Parallel Processing Implementing Sequential Consistency In CacheBased Systems +
 

Summary: ­­ ­­
To appear in the Proceedings of the 1990 International Conference on Parallel Processing
Implementing Sequential Consistency In Cache­Based Systems +
Sarita V. Adve
Mark D. Hill
Computer Sciences Department
University of Wisconsin
Madison, Wisconsin 53706
ABSTRACT
A model for shared­memory systems commonly
(and often implicitly) assumed by programmers is that
of sequential consistency. For implementing sequential
consistency in a cache­based system, it is widely
believed that (1) implementing strong ordering is
sufficient and (2) restricting a processor to one shared­
memory reference at a time is practically necessary.
In this paper we show that both beliefs are false.
First, we prove that (1) is false with a counter­example.
Second, we argue that (2) is false by giving sufficient
conditions and an implementation that allow a processor

  

Source: Adve, Sarita - Department of Computer Science, University of Illinois at Urbana-Champaign
Hill, Mark D. - Department of Computer Sciences, University of Wisconsin at Madison

 

Collections: Computer Technologies and Information Sciences