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VHDL course Lab Session 1

Summary: VHDL course
Lab Session 1
E.M. Aboulhamid
1 Objectives
The objective of this exercise is to give some practical experience of the use of VHDL in
simple modeling situations and to gain some familiarity with your favorite set of
simulation tools
2 Tutorial
If you are using ModelSim environment, run the tutorial starting page 97 of the tutorial
(help::EE documentation::EE Tutorial)
Examine the code you are using and try to understand it.
3 Running a behavioral model
Re-run the dataflow model of the full adder with the testbench. Examine the log of the
list of signals. Understand the delta delay mechanism.
4 Development of a structural model
4.1 Development steps
o Create a folder for a project.
o Create a library work once.
o Develop and compile all your design units.
o Load and simulate your design.


Source: Aboulhamid, El Mostapha - Département d'Informatique et recherche opérationnelle, Université de Montréal


Collections: Engineering