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A Fast Low-Power Modulo 2n + 1 Multiplier
 

Summary: 1
A Fast Low-Power Modulo 2n
+ 1 Multiplier
Rajashekhar Modugu, Nohpill Park, Yong-Bin Kim and Minsu Choi
Abstract
Modulo 2n
+1 multiplier is one of the critical components in applications in the area of digital signal
processing, data encryption and residue arithmetic that demand high-speed and low-power operation. In
this paper, an efficient hardware architecture of modulo 2n
+ 1 multiplier is proposed and validated to
address the demand. The proposed modulo 2n
+1 multiplier has three major functional modules including
partial products generation module, partial products reduction module and final stage addition module.
The proposed modulo 2n
+1 multiplier uses novel compressor designs and sparse tree adders as primitive
building blocks for fast low-power operation. The partial products reduction module is completely
redesigned using the novel compressors and the final addition module is implemented using a new less
complex sparse tree based inverted end-around-carry adder. The resulting modulo 2n
+ 1 multiplier is
implemented in standard CMOS cell technology and compared both qualitatively and quantitatively with

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering