Summary: CONCURRENT DESIGN ERROR SIMULATION FOR HIGH-LEVEL
MICROPROCESSOR IMPLEMENTATIONS
Jorge Campos
University of California
One Shields Ave
Davis, CA 95616
jcampos@ece.ucdavis.edu
Hussain Al-Asaad
University of California
One Shields Ave
Davis, CA 95616
halasaad@ece.ucdavis.edu
Abstract -- A high-level concurrent design
error simulator that can handle various design
error/fault models is presented. The simulator
is a vital building block of a new promising
method of high-level testing and design vali-
dation that aims at explicit design error/fault
modeling, design error simulation, and model-
directed test pattern generation. We first de-

Source: Al-Asaad, Hussain - Department of Electrical and Computer Engineering, University of California, Davis

Collections: Computer Technologies and Information Sciences