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An Efficient Technique for Preventing Single Event Disruptions in Synchronous and Reconfigurable Architectures
 

Summary: An Efficient Technique for Preventing Single Event Disruptions in Synchronous
and Reconfigurable Architectures
Sajid Baloch1,2
, Tughrul Arslan1,2
, Adrian Stoica1,3
1: School of Electronics & Engineering. University of Edinburgh, King's Buildings, Mayfield Rd, EH9 3JL, UK
2: Institute for System Level Integration, The Alba Campus, The Alba Centre, Livingston, EH54 7EG, UK)
3: NASA, Jet Propulsion Laboratory, 4800 Oak Grove Drive, Pasadena, CA 91109, USA
ABSTRACT
This paper presents a unique SEU (single Event Upset)
mitigation technique based upon Temporal Data Sampling
for synchronous circuits and configuration bit storage for
programmable devices. The design technique addresses both
conventional static SEUs and SETs (Single Event
Transients) induced errors that can result in data loss for any
synchronous and reconfigurable architecture. The proposed
scheme may be employed in circuits to eliminate all SEUs
and SETs for performance critical applications.. This
approach permits FPGAs and other microcircuits with deep
submicron feature size to be used in hostile space

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering