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Appears in Workshop on Complexity-Effective Design, 28th ISCA, Gothenburg, Sweden, June 2001 1 The Span Cache: Software Controlled Tag Checks and Cache Line Size
 

Summary: Appears in Workshop on Complexity-Effective Design, 28th ISCA, G¨othenburg, Sweden, June 2001 1
The Span Cache: Software Controlled Tag Checks and Cache Line Size
Emmett Witchel and Krste Asanovi´c
MIT Laboratory for Computer Science, Cambridge, MA 02139
witchel|krsteˇ @lcs.mit.edu
Abstract
The span cache is a hardware-software design for a new
kind of energy-efficient microprocessor data cache which
has two key features. The first is direct addressing which
allows software to access cache data without the hard-
ware performing a cache tag check. These tag-unchecked
loads and stores save the energy of performing a tag check
when the compiler can guarantee an access will be to the
same line as an earlier access. The second key feature is
software controlled line size. This lets the compiler specify
how much data to fetch on a miss, allowing greater cache
utilization and reducing memory bandwidth requirements.
Two possible hardware implementations of software con-
trolled line size are sketched and discussed.
1 Introduction

  

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group
Witchel, Emmett - Department of Computer Sciences, University of Texas at Austin

 

Collections: Computer Technologies and Information Sciences