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Summary: Segmentation Strategies for Low Power Implementation of Digital Filters
T. Arslan and A. T. Erdogan
University of Edinburgh,
Department of Electronics 8z Electrical Engineering,
Edinburgh EH9 3JL,
Scotland,UK.
E-mail: arslan0ee.ed.ac.uk ate0ee.ed.ac.uk
Abstract
Thispaper describes a generic algorithmfor low power
implementation of digital filers. The algorithm reduces
power through a reduction in the amount of switched
capacitance within the multiplier section of the filter. This
reduction in turn is achieved through the segmentation of a
given coeficient into two primitive sub-components. The
algorithm is suitable for prototyping as an Intellectual
Propeq core with high degree of parameterisability. Hence
making the core extremely valuablefor rapid system-on-chip
implementation for multi-medidwireless applications. The
paper describes the algorithm, its adaptability to different
representation formats, and provides results which show
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