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Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency
 

Summary: Zero-Cycle Loads: Microarchitecture Support for
Reducing Load Latency
Todd M. Austin Gurindar S. Sohi
University of Wisconsin-Madison
1210 W. Dayton Street
Madison, WI 53706
faustin,sohig@cs.wisc.edu
Abstract
Untolerated load instruction latencies often have a significant
impact on overall program performance. As one means of miti-
gating this effect, we present an aggressive hardware-based mech-
anism that provides effective support for reducing the latency of
load instructions.
Through the judicious use of instruction predecode, base regis-
ter caching, and fast address calculation, it becomes possible to
complete load instructions up to two cycles earlier than traditional
pipeline designs. For a pipeline with one cycle data cache access,
this results in what we term a zero-cycle load. A zero-cycle load
produces a result prior to reaching the execute stage of the pipeline,
allowing subsequent dependent instructions to issue unfettered by

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan

 

Collections: Engineering; Computer Technologies and Information Sciences