Summary: The Energy Efficiency of IRAM Architectures
Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos Kozyrakis,
Bruce McGaughy, David Patterson, Tom Anderson, Katherine Yelick
Computer Science Division, University of California--Berkeley
Abstract
Portable systems demand energy efficiency in order to maxi­
mize battery life. IRAM architectures, which combine DRAM and
a processor on the same chip in a DRAM process, are more energy
efficient than conventional systems. The high density of DRAM per­
mits a much larger amount of memory on­chip than a traditional
SRAM cache design in a logic process. This allows most or all
IRAM memory accesses to be satisfied on­chip. Thus there is much
less need to drive high­capacitance off­chip buses, which contribute
significantly to the energy consumption of a system. To quantify this
advantage we apply models of energy consumption in DRAM and
SRAM memories to results from cache simulations of applications
reflective of personal productivity tasks on low power systems. We
find that IRAM memory hierarchies consume as little as 22% of the
energy consumed by a conventional memory hierarchy for memory­
intensive applications, while delivering comparable performance.

Source: Anderson, Tom - Department of Computer Science and Engineering, University of Washington at Seattle
Yelick, Katherine - Department of Electrical Engineering and Computer Sciences, University of California at Berkeley

Collections: Computer Technologies and Information Sciences