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Minimizing Register Requirements for Synchronous Circuits Derived Using Software Pipelining Techniques
 

Summary: Minimizing Register Requirements for Synchronous Circuits
Derived Using Software Pipelining Techniques
Noureddine Chabini1, El Mostapha Aboulhamid1, Yvon Savaria2
1: LASSO, DIRO, Université de Montréal C.P.6128, Suc. Centre ville, Montréal, Qc, Canada, H3C 3J7.
Email:{chabinin, aboulham}@iro.umontreal.ca
2: GRM, DGEGI, École Polytechnique de Montréal, C.P. 6079, Suc. Centre-ville, Montréal, Qc, Canada,
H3C 3A7. Email: savaria@vlsi.polymtl.ca
Abstract
A method based on software pipelining has been recently
proposed to optimize mono-phase clocked sequential circuits. The
resulting circuits are multi-phase clocked sequential circuits,
where all clocks have the same period. To preserve functionality of
the original circuit, registers must be placed according to a correct
schedule. This schedule also ensures the maximum throughput. In
that method, it is question of (1) how to determine a schedule that
requires the minimum number of registers, and (2) how to place
these registers optimally. In this paper, problems (1) and (2) are
tackled simultaneously. More precisely, we deal with the problem
of determining schedules with the minimum register requirements,
where the optimal register placement is done during the schedule

  

Source: Aboulhamid, El Mostapha - Département d'Informatique et recherche opérationnelle, Université de Montréal

 

Collections: Engineering