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Contributed article A fast neural-network algorithm for VLSI cell placement

Summary: Contributed article
A fast neural-network algorithm for VLSI cell placement
Cevdet Aykanata,
*, Tevfik Bultanb
, Ismail Haritaoglub
Department of Computer Engineering, Bilkent University, Ankara, TR-06533, Turkey
Department of Computer Science, University of Maryland, College Park, MD 20742, USA
Received 4 July 1997; accepted 15 May 1998
Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate
Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are
known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This
algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization
problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To
demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the
layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison
with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance
evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed


Source: Aykanat, Cevdet - Department of Computer Engineering, Bilkent University


Collections: Computer Technologies and Information Sciences