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Liberty Queues for EPIC Architectures Thomas B. Jablin1 Yun Zhang1 James A. Jablin2 Jialu Huang1 Hanjun Kim1 David I. August1
 

Summary: Liberty Queues for EPIC Architectures
Thomas B. Jablin1 Yun Zhang1 James A. Jablin2 Jialu Huang1 Hanjun Kim1 David I. August1
1Department of Computer Science, Princeton University
2Department of Computer Science, Brown University
{tjablin,yunzhang,jialuh,hanjunk,august}@princeton.edu jjablin@cs.brown.edu
Corresponding Author: Thomas B. Jablin
Liberty Queues for EPIC Architectures
Thomas B. Jablin Yun Zhang James A. Jablin2 Jialu Huang Hanjun Kim David I. August
Department of Computer Science, Princeton University 2Department of Computer Science, Brown University
{tjablin,yunzhang,jialuh,hanjunk,august}@princeton.edu jjablin@cs.brown.edu
Abstract
Core-to-core communication bandwidth is critical for high-performance pipeline-parallel programs. Hardware
communication queues are unlikely to be implemented and are perhaps unnecessary. This paper presents Liberty
Queues, a high-performance lock-free software-only ring buffer, and describes the porting effort from the
original x86-64 implementation to IA-64. Liberty Queues achieve a bandwidth of 500 MB/s between unrelated
processors on a first generation Itanium 2, compared with 281 MB/s on modern Opterons and 430 MB/s on
modern Xeons claimed by related works. We present bandwidth results for seven different multicore and
multiprocessor systems, as well as a sensitivity analysis.
Categories and Subject Descriptors D.1.3 [Programming Techniques]: Concurrent Programming--Parallel
Programming

  

Source: August, David - Department of Computer Science, Princeton University

 

Collections: Computer Technologies and Information Sciences