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Architecting a Reliable CMP Switch Architecture
 

Summary: Architecting a Reliable CMP Switch
Architecture
KYPROS CONSTANTINIDES, STEPHEN PLAZA, JASON BLOME,
VALERIA BERTACCO, SCOTT MAHLKE, and TODD AUSTIN
University of Michigan
and
BIN ZHANG and MICHAEL ORSHANSKY
University of Texas at Austin
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as
devices become subject to extreme process variation, particle-induced transient errors, and tran-
sistor wear-out. Unless these challenges are addressed, computer vendors can expect low yields
and short mean-times-to-failure. In this article, we examine the challenges of designing complex
computing systems in the presence of transient and permanent faults. We select one small aspect
of a typical chip multiprocessor (CMP) system to study in detail, a single CMP router switch. Our
goal is to design a BulletProof CMP switch architecture capable of tolerating significant levels of
various types of defects. We first assess the vulnerability of the CMP switch to transient faults. To
better understand the impact of these faults, we evaluate our CMP switch designs using circuit-
level timing on detailed physical layouts. Our infrastructure represents a new level of fidelity in
architectural-level fault analysis, as we can accurately track faults as they occur, noting whether
they manifest or not, because of masking in the circuits, logic, or architecture. Our experimental

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan
Bertacco, Valeria - Department of Electrical Engineering and Computer Science, University of Michigan

 

Collections: Computer Technologies and Information Sciences; Engineering