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Copyright 1997 IEEE. Published in the Proceedings of Micro-30, December 1-3, 1997 in Research Triangle Park, North Carolina. Per-sonal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional
 

Summary: Copyright 1997 IEEE. Published in the Proceedings of Micro-30, December 1-3, 1997 in Research Triangle Park, North Carolina. Per-
sonal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or
for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in
other works, must be obtained from IEEE. Contact: Manager, Copyrights and Permissions / IEEE Service Center / 445 Hoes lane / P. O.
Box 1331 / Piscataway, NJ 08855-1331, USA. Telephone: + Intl. 908-562-3966.
On High-Bandwidth Data Cache Design for Multi-Issue
Processors
Abstract
Highly aggressive multi-issue processor designs of the
past few years and projections for the next decade require
that we redesign the operation of the cache memory sys-
tem. The number of instructions that must be processed
(including incorrectly predicted ones) will approach 16 or
more per cycle. Since memory operations account for
about a third of all instructions executed, these systems
will have to support multiple data references per cycle. In
this paper, we explore reference stream characteristics to
determine how best to meet the need for ever increasing
access rates. We identify limitations of existing multi-
ported cache designs and propose a new structure, the

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan

 

Collections: Engineering; Computer Technologies and Information Sciences