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A Fully Asynchronous Superscalar Architecture D. K. Arvind and Robert D. Mullins
 

Summary: A Fully Asynchronous Superscalar Architecture
D. K. Arvind and Robert D. Mullins
Division of Informatics
The University of Edinburgh
Mayfield Road, Edinburgh EH9 3JZ, Scotland.
dka,rdm@dcs.ed.ac.uk
Abstract
An asynchronous superscalar architecture is presented
based on a novel architectural feature called instruction
compounding. This enables efficient dynamic scheduling
and forwarding of data based on local information, while
maintaining the advantages of asynchrony in terms of ex-
ploiting actual delays. Results are presented in which stat-
ically and dynamically compounded architectures are com-
pared against an equivalent synchronous superscalar archi-
tecture.
1. Introduction
The design of high clock frequency processors leads to
considerable physical problems in distributing the clock
signal, high power dissipation and poor electromagnetic

  

Source: Arvind, D. K. - School of Informatics, University of Edinburgh

 

Collections: Computer Technologies and Information Sciences