| | |
Summary: A Novel All-Digital Phase-Locked Loop With Ultra
Fast Frequency and Phase Acqusition
Jun Zhao
Department of Electrical and Computer Engineering
Northeastern University
Boston, USA
jzhao@ece.neu.edu
Yong-Bin Kim
Department of Electrical and Computer Engineering
Northeastern University
Boston, USA
ybk@ece.neu.edu
Abstract-- An all-digital phase-locked loop with fast acquisition
and low power DCO is presented. The proposed ADPLL is
designed with a unique lock-in process by employing a time-to-
digital converter. Both the frequency of the reference clock and
the delay between DCO output and DCO clock are measured. A
carefully designed reset process reduces the phase lock into two
cycles. The ADPLL was implemented using a 0.9V 32nm
practical transistor model (PTM). The simulation results show
|
