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Abstract Modern performance-oriented ISAs, such as RISC and VLIW, only expose to software features that impact the critical path through computation. Pipelined
 

Summary: 

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Abstract Modern performance-oriented ISAs, such as RISC and VLIW, only expose to
software features that impact the critical path through computation. Pipelined
microprocessor implementations hide most of the microarchitectural work per-
formed in executing instructions. Therefore, there is no incentive to expose these
micro-operations, and their energy consumption is hidden from software.
This work presents energy-exposed hardware-software interfaces to give soft-
ware more fine-grain control over energy-consuming microarchitectural opera-
tions. We introduce software restart markers to make temporary processor state
visible to software without complicating hardware exception management. This
technique can enable a wide variety of energy optimizations. We implement
exposed bypass latches which allow the compiler to eliminate register file traf-
fic by directly targeting the processor bypass latches. Another technique, tag-
unchecked loads and stores, allows software to access cache data without a hard-

  

Source: Asanovi, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

 

Collections: Computer Technologies and Information Sciences