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748 IEEE TRANSACTIONS ON MAGNETICS, VOL. 37, NO. 2, MARCH 2001 VLSI Architectures for Iterative Decoders in
 

Summary: 748 IEEE TRANSACTIONS ON MAGNETICS, VOL. 37, NO. 2, MARCH 2001
VLSI Architectures for Iterative Decoders in
Magnetic Recording Channels
Engling Yeo, Student Member, IEEE, Payam Pakzad, Borivoje Nikolicī, Member, IEEE, and
Venkat Anantharam, Fellow, IEEE
Abstract--VLSI implementation complexities of soft-input
soft-output (SISO) decoders are discussed. These decoders are
used in iterative algorithms based on Turbo codes or Low Density
Parity Check (LDPC) codes, and promise significant bit error
performance advantage over conventionally used partial-response
maximum likelihood (PRML) systems, at the expense of increased
complexity. This paper analyzes the requirements for compu-
tational hardware and memory, and provides suggestions for
reduced-complexity decoding and reduced control logic. Serial
concatenation of interleaved codes, using an outer block code with
a partial response channel acting as an inner encoder, is of special
interest for magnetic storage applications.
Index Terms--Iterative decoders, LDPC codes, magnetic
recording, turbo codes, VLSI architectures.
I. INTRODUCTION

  

Source: Anantharam, Venkat - Department of Electrical Engineering and Computer Sciences, University of California at Berkeley
Nikolic, Borivoje - Department of Electrical Engineering and Computer Sciences, University of California at Berkeley

 

Collections: Engineering