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Summary: Abstract
Multiple Input Multiple Output (MIMO) wireless
technology involves highly complex signal processing
which is directly related to increased power and area
consumption in VLSI architecture. This paper proposes
an enhanced dual strategy based VLSI architecture
developed for computing the pseudo inverse of
augmented channel matrix used in MIMO systems. The
architecture concurrently addresses algorithmic
optimization of number of multipliers while at the same
time allowing for intelligent selective clock gating to
disable the clock to those portions of the architecture
that remain inactive during period of computation.
Results indicate overall 36% power and 31% area
reduction compared to previous architecture without
degrading the BER performance.
1. Introduction
Multiple Input - Multiple Output (MIMO) wireless
communication is a new technology that promises to
remove the limits of wireless networks by providing
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