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Figure 1. DICE cell proposed in [6] A Novel Design Technique for Soft Error
 

Summary: Figure 1. DICE cell proposed in [6]
A Novel Design Technique for Soft Error
Hardening of Nanoscale CMOS Memory
Sheng Lin, Yong-Bin Kim and Fabrizio Lombardi
Department of Electrical and Computer Engineering
Northeastern University
Boston, MA, USA
Abstract--Tolerance to soft errors has become a strict
requirement in today's nanoscale CMOS designs. This
paper proposes a new hardening design technique for
CMOS memory cell at 32nm feature size. The proposed
hardened memory cell overcomes the problems associated
with the previous designs by utilizing novel access and
refreshing mechanisms. Simulation shows that the data
stored in the proposed hardened memory cell does not
change even for a transient pulse with more than two times
higher charge than the conventional memory cell and
achieves a 55% reduction in power delay product compared
to the DICE cell, thus achieving a significant improvement
in soft error tolerance. The extensive HSPICE simulations

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering