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DLX_CPU mem_ROM bridge mem_RAM
 

Summary: DLX_CPU mem_ROM
bridge mem_RAM
ring_device[i]
ring_device[i+1]ring_device[i-1]
connected to previous DLX bridge connected to next DLX bridge
SystemC Performance Evaluation using a Pipelined DLX Multiprocessor
L. Charest, E.M. Aboulhamid C. Pilkington, P. Paulin
DIRO, Université de Montréal
2920 Ch. de la Tour
CP6128 Centre-Ville
Montréal, Qc, Canada H3C 3J7
{aboulham, charestlu}@iro.umontreal.ca
System-on-chip Platform Automation
STMicroelectronics, Central R&D
16 Fitzgerald Road, Suite 300
Nepean Ontario K2H 8R6 CANADA
{chuck.pilkington, Pierre.paulin}@st.com
1. Introduction
The objective of this work is to evaluate the
performance of SystemC [1] in modeling a pipelined

  

Source: Aboulhamid, El Mostapha - Département d'Informatique et recherche opérationnelle, Université de Montréal

 

Collections: Engineering