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Summary: Abstract
To achieve high instruction throughput, instruction
schedulers must be capable of producing high-quality
schedules that maximize functional unit utilization while at
the same time enabling fast instruction issue logic. Many
solutions exist to the scheduling problem, ranging from
compile-time to run-time approaches. Compile-time solu-
tions feature fast and simple hardware, but at the expense
of conservative schedules. Dynamic schedulers produce
high-quality schedules that incorporate run-time informa-
tion and dependence speculation, but implementing these
schedulers requires complex circuits that can slow proces-
sor clock speeds.
In this paper, we present the Cyclone scheduler, a
novel design that captures the benefits of both compile-
and run-time scheduling. Our approach utilizes a list-
based single-pass instruction scheduling algorithm, imple-
mented by hardware at run-time in the front end of the pro-
cessor pipeline. Once scheduled, instructions are injected
into a timed queue that orchestrates their entry into execu-
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