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Abstract--We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level
 

Summary: 1
Abstract--We present a Mutation-based Validation Paradigm
(MVP) technology that can handle complete high-level
microprocessor implementations and is based on explicit design
error modeling, design error simulation, and model-directed test
vector generation. We first present a control-based coverage
measure that is aimed at exposing design errors that incorrectly
set control signal values. We then describe MVP's high-level
concurrent design error simulator that can handle various
modeled design errors. We then present fundamental techniques
and data structures for analyzing high-level circuit
implementations and present various optimizations to speed-up
the processing of data structures and consequently speed up
MVP's overall test generation process. We next introduce a new
automatic test vector generation technique for high-level
hardware descriptions that generates a test sequence by
efficiently solving constraints on multiple finite state machines.
To speed up the test generation, MVP is empowered by learning
abilities via profiling various aspects of the test generation
process. Our experimental results show that MVP's learning

  

Source: Al-Asaad, Hussain - Department of Electrical and Computer Engineering, University of California, Davis

 

Collections: Computer Technologies and Information Sciences