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Abstract--Fault collapsing is the process of reducing the number of faults by using redundance and equiva-
 

Summary: 1
Abstract--Fault collapsing is the process of reducing
the number of faults by using redundance and equiva-
lence/dominance relationships among faults. Exact glo-
bal fault collapsing can be easily applied locally at the
logic gates, however, it is often ignored for library
modules due to its high demand of resources such as
execution time and/or memory. In this paper, we
present an efficient and exact global fault collapsing
method for library modules that uses both binary deci-
sion diagrams and fault simulation with random vec-
tors. Experimental results show that the new method
reduce the number of faults drastically with feasible
resources and produce significantly better results than
existing approaches.
Keywords: Global fault collapsing, fault simulation,
testing, combinational circuits.
1 INTRODUCTION
To test a digital circuit, an automatic test pattern
generation (ATPG) tool generates a test set that targets

  

Source: Al-Asaad, Hussain - Department of Electrical and Computer Engineering, University of California, Davis

 

Collections: Computer Technologies and Information Sciences