Summary: Evaluation of a Stall" Cache:
An E cient Restricted On-chip Instruction Cache
Klaus Erik Schauser
Krste Asanovi c
David A. Patterson
Computer Science Division, EECS Department
University of California, Berkeley
Berkeley, CA 94720
Edward H. Frank
Sun Microsystems
Mountain View, California
Abstract
In this report we compare the cost and performance of
a new kind of restricted instruction cache architecture
| the stall cache | against several other conventional
cache architectures. The stall cache minimizes the size
of an on-chip instruction cache by caching only those
instructions whose instruction fetch phase collides with
the memory access phase of a preceding load or store
instruction.

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)

Collections: Computer Technologies and Information Sciences