Summary: Throughput-Effective On-Chip Networks for Manycore Accelerators
Ali Bakhoda
ECE Department
University of British Columbia
Vancouver, Canada
Email: bakhoda@ece.ubc.ca
John Kim
CS Department
KAIST
Daejeon, Korea
Email: jjk12@kaist.edu
Tor M. Aamodt
ECE Department
University of British Columbia
Vancouver, Canada
Email: aamodt@ece.ubc.ca
Abstract--As the number of cores and threads in manycore
compute accelerators such as Graphics Processing Units (GPU)
increases, so does the importance of on-chip interconnec-
tion network design. This paper explores throughput-effective

Source: Aamodt, Tor - Department of Electrical and Computer Engineering, University of British Columbia

Collections: Engineering; Computer Technologies and Information Sciences