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To generate tests for a digital circuit, the test generation tool is initially provided with the circuit description in a
 

Summary: ABSTRACT
To generate tests for a digital circuit, the test generation
tool is initially provided with the circuit description in a
netlist format and then it creates a list of faults that need to
be targeted for detection. For large circuits, the number of
faults can become very large. It is thus beneficial to mini-
mize the number of faults whenever possible. Fault col-
lapsing is the process of reducing the number of faults by
using equivalence and dominance relationships among
faults. Exact fault collapsing can be easily applied locally
at the logic gates, however, it is not feasible to apply it glo-
bally for large circuits. In this paper, we present an approx-
imate global fault collapsing technique that is based on the
simulation of random vectors. Experimental results show
that our method reduces the number of faults drastically
with feasible resources.
Keywords: Global fault collapsing, simulation, physi-
cal fault testing.
1 INTRODUCTION
To test a digital circuit, an automatic test pattern

  

Source: Al-Asaad, Hussain - Department of Electrical and Computer Engineering, University of California, Davis

 

Collections: Computer Technologies and Information Sciences